1) Field of the Invention
This invention relates to a fabrication method for an electrically programmable read-only, split gate MONOS (Metal/polysilicon Oxide Nitride Oxide silicon) memory having a composite of oxide-nitride-oxide (ONO) underneath the control gate in which high efficiency of channel hot electron injection from channel to silicon nitride can be achieved.
2) Description of the Prior Art
Side wall polysilicon gates with MONOS structure was reported by Kuo-Tung Chang et al in the paper "A New SONOS Memory Using Source Side Injection for Programming" in IEEE Electron Letter, Vol. 19, No. 7, July 1998. In the structure, a channel potential drop is formed at the gap between the sidewall gate and the select gate (word) such that the channel electron are accelerated in this gap region and become hot enough to inject into the oxide-nitride-oxide layer (trapped in the nitride layer) underneath the sidewall gate.
As shown in FIG. 1a, the typical sidewall process forms spacers on both sides of the word gate. This source side hot electron injection, which is commonly used in floating gate nonvolatile memory was first time employed for MONOS memory programming by Kuo-Tung Chang et al. In the similar structure, when the gate channel is reduced to less than 40 nm (Kuo-Tung Chang et al's channel length is about 200 nm), a new and much more efficient injection mechanism (Ballistic injection) takes over instead of source side injection as predicted in the S. Ogura U.S. Pat. No. 5,780,341. The ballistic injection mechanism has been proved by S. Ogura in the paper "Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash" in IEDM 1998, pp. 987. As shown in FIG. 1b, when the control gate channel length is even 100 nm (Kuo-Tung Chang et al's channel length is twice as large that is 200 nm), the injection mechanism becomes source side injection which requires high floating gate potential above 5 volts. However, when the memory gate becomes less than 40 nm and the channel is properly doped, a ballistic injection device can be formed.
Because most of the embedded logic applications utilize only one side of polysilicon, one memory element word gate, the unused side spacer is removed or disabled. It is possible to disable the effect of unwanted side of control gate by implants of N- dopants such as Arsenic or Phosphorus under the unwanted gate using a block mask, prior to formation of the sidewall spacer, in order to short the unwanted gate to the adjacent diffusion. In another approach, the unwanted polysilicon gate material is used to fill the self aligned contact, as shown by Seiki Ogura in U.S. Pat. No. 5,780,341.
However, in integrating the Split Gate MONOS Transistor and high voltage devices in logic technology an optimum process which provides simplicity and reliability has to be considered. The logic gates, high voltage gates, and memory gates are all dimensionally critical and their relative positions are important. Therefore, it is preferable to define all three types of devices together at once rather than by separate masking processes. However, this preferred idea faces difficulty once the logic gate oxide becomes thin as 3.0 nm in the 0.18 micron feature size technology.
If the logic gates are formed prior to the side wall gates, the side wall spacers on the logic gates need to be removed, and the edges of the logic gate oxide could be damaged during the removal. On the other hand, if the logic gates are defined by a second critical mask after the memory word gates and spacer gates have been defined and formed, the damage to the logic gates' oxide during spacer removal, can be avoided. But the second approach requires two critical masks to define memory word gate and logic gate separately.